Jobs at Rivos
Fast-moving startup focused on FPGA design and enabling brand-new hardware.. Check all open positions at Rivos.
Open positions at Rivos
📍 All job functions
Fast-moving startup focused on FPGA design and enabling brand-new hardware.. Check all open positions at Rivos.
🇺🇸Added a day ago
Post-Silicon Engineering Program Manager
🇺🇸Added 19 days ago
Senior Member of Technical Staff
DFTDFDSoC
🇺🇸Added 19 days ago
Silicon DDR Bringup and Validation Engineer
DDRSOC designC/C++PythonVerilog simulationwaveform viewersemulationlab instruments
🇹🇼Added 21 days ago
UPF Engineer
ASIC design methodologypower definitionpower intent definitionRTL2GDS flowRTL simequivalencesynthesisP&Rintent checkingTcl + 5
🇺🇸Added a month ago
NOC Logic Design Engineer
Network on ChipRisc-VSystem VerilogEDA tools
🇺🇸Added a month ago
Junior Power-Management Architect
CPU/GPU/SoC architecturesimulatorsclock gatingpower gatingDVFSC/C++PythonVerilogSystemVerilog
🇬🇧🇫🇷🇨🇭🇩🇰🇩🇪Added 2 months ago
Software Packaging Engineer
Pythonbashaptdnf/yumpipCondaOpen Source
🇺🇸Added 2 months ago
Member of Technical Staff
PythonC++RISC-V architectureLinux kernelMachine learning
🇺🇸Added 3 months ago
Deep Learning Systems Architect
Deep learningPythonC++CUDAHIPOpenCLRTLPerformance simulatorsComputer architectureMemory hierarchy + 2
🇹🇼Added 3 months ago
Silicon Engineering Program Manager
CPUSOCdata processing engines
🇮🇳Added 3 months ago
Silicon Engineering Program Manager
CPUSOCdata processing engines
🇺🇸Added 3 months ago
Accelerator Microarchitecture Performance Modeling Engineer
C/C++Machine learningC++
🇺🇸Added 4 months ago
Silicon Physical Design Verification Manager
CalibrePegasustclPython
🇬🇧Added 4 months ago
Logic Design Engineer
System VerilogPythonArithmetic UnitsNoCFabric DesignCPU Load/StoreScheduling Logic
🇺🇸🇮🇳🇬🇧🇹🇼Added 4 months ago
SOC Emulation Engineer
Verilog/SystemVerilogC/C++PalladiumZebuVeloceProtiumHAPSQEmuPythonTCL
🇬🇧🇫🇷🇨🇭🇩🇰🇩🇪Added 4 months ago
LLVM Backend Senior Engineer
LLVMC++Open Source
🇹🇼Added 4 months ago
Silicon PDV Engineering Manager
Risc-VDRCLVSESDTCLPythonCalibrePegasus
🇮🇳Added 5 months ago
Silicon Verification Engineer
Risc-VAI/analytics acceleratorComputer architectureCPU/GPU/Accelerator DVSystem VerilogC++PythonHW-SW co-simulationEmulationTest benches + 2
🇺🇸Added 5 months ago
Silicon PCIe Bringup and Validation Engineer
PCIeC/C++PythonVerilog simulationemulation
🇹🇼Added 5 months ago
CPU Design Verification Engineer
SystemVerilogC/C++PythonTCLFormal Verification
🇺🇸Added 5 months ago
Senior Memory Design Engineer
SRAM memoriesRegister file memoriescompiled memoriesFinFET technology nodescustom circuit designDFMLEC toolsmask designersdesign collateralfloorplanning + 7
🇺🇸Added 5 months ago
Senior Memory Design Engineer
CPUSoCFinFET technology nodesDevice physicsProcess technologyMask designLEC toolsDFMFloorplanningPlacement + 4
🇺🇸Added 5 months ago
CPU Microarchitecture & Logic Design
System VerilogC/C++PerlPythonC++
🇹🇼Added 5 months ago
Sr. ATE Test Engineer
Automatic Test EquipmentAdvantest 93KTeradyne Uflex
🇹🇼Added 5 months ago
Senior Memory Design Engineer
custom SRAM memoriesRegister file memoriescompiled memoriesFinFET technology nodes
🇺🇸Added 5 months ago
Senior Memory Design Engineer
SRAM memoriesRegister file memoriesCompiled memoriesStandard cellsFinFET technology nodesDevice physicsProcess technologyLEC toolsMask designersDFM + 5
🇺🇸Added 5 months ago
Post-Silicon Power Engineer
AssemblyCPythonshell programminglab equipmentEnterprise
🇺🇸Added 5 months ago
Logic Design Engineer
System VerilogPythonSynthesisPhysical DesignComputer ArchitectureArithmetic UnitsNoCFabric DesignCPU Load/StoreScheduling Logic
🇺🇸Added 5 months ago
Coherent Interconnect Microarchitecture & Logic Design
SystemVerilogVerilogAMBAAXICHIACETilelinkAPBSystem cachesMesh + 3
🇺🇸Added 5 months ago
Accelerator Logic Design Engineer
System VerilogPythonNoCFabric DesignCPU Load/StoreScheduling Logic
🇹🇼Added 5 months ago
SOC Physical Design Verification Engineer
Siemens CalibretclPython
🇺🇸Added 5 months ago
Accelerator Logic Design Engineer
System VerilogPythonCPU load/storescheduling logicNoCfabric designarithmetic units
🇺🇸Added 5 months ago
Coherent Interconnect Microarchitecture & Logic Design
RISC-VAMBAAXICHIACETilelinkAPBSystemVerilogVerilogRTL + 4
🇺🇸Added 5 months ago
Microarchitecture & Logic Design Engineer
RISC-VAMBAAXICHIACETilelinkAPBSystemVerilogVerilogRTL coding + 3
🇹🇼Added 5 months ago
SOC Static Timing Analysis Engineer
ASIC timing constraintstiming EDA toolscrosstalk delaynoise glitchPOCVIR-STAcsh/bashTCLPython
🇮🇳Added 5 months ago
CPU Design Verification Engineer
RISC-V CPUSystemVerilogC/C++PythonTCLsimulatorswaveform viewersbuild and run automationcoverage collectionformal verification + 1
🇺🇸Added 5 months ago
LLVM Backend Senior Engineer
LLVMSIMTC++Open Source
🇺🇸Added 5 months ago
CPU Performance Modeling Engineer
C/C++PerlPythonSystemVerilog
Internship🇺🇸Added 5 months ago
CPU Performance Modeling Intern
RISCVC/C++PerlPythonSystemVerilog
🇺🇸Added 5 months ago
CPU Design Verification Engineer
SystemVerilogC/C++PythonTCLformal verification
🇺🇸Added 5 months ago
Accelerator Performance Architect
C/C++PythonSystem VerilogC++
🇺🇸Added 5 months ago
CPU Design Verification Engineer
SystemVerilogC/C++PythonTCLFormal verification
🇺🇸Added 6 months ago
Senior Memory Design Engineer
custom SRAM memoriesRegister file memoriescompiled memoriescircuit designcircuit simulationequivalence checkingPPA trade off analysistimingdevice physicsprocess technology + 17
🇺🇸Added 6 months ago
Die-to-Die Interconnect Microarchitecture & Logic Design
UCIePCIeAMBAAXICHIACETilelinkMESIMESIFMOESI + 5
🇺🇸Added 6 months ago
Interconnect Microarchitecture & Logic Design
RISC-VAMBAAXICHIACETilelinkAPBSystemVerilogVerilogsimulators + 2
🇺🇸Added 6 months ago
Logic Design Engineer
System VerilogPythonArithmetic UnitsNoCFabric DesignCPU Load/StoreScheduling Logic
🇺🇸Added 6 months ago
CPU Microarchitecture & Logic Design
CPU microarchitecturelogic designmemory managementload/store pipelinecachepower managementdebug featuresbus interface designsSystem Verilogsimulators + 6
🇺🇸Added 7 months ago
Senior Memory Design Engineer
custom SRAM memoriesRegister file memoriescompiled memoriescircuit designcircuit simulationequivalence checkingPPA trade off analysistimingFinFET technology nodesdevice physics + 12
🇮🇳Added 7 months ago
UPF Engineer
UPFASIC design methodologyRTL2GDS flowTclPythonCAD
🇮🇳Added 7 months ago
Senior Memory Design Engineer
custom SRAM memoriesRegister file memoriescompiled memoriesRTL-GDSFinFET technology nodesdevice physicsprocess technologymask designautomationpost-silicon test + 8