Sr Staff ASIC Design Verification

• Responsible for verification of SOCs using UVM/OVM methodologies
• Verification planning, maintenance, feature extraction, verification test case and checker development
• Develop efficient, reusable state-of-the-art verification environments and testbench structures
• Initiate and participate in review meetings with design and verification engineers
• Mentor junior engineers in the team

Requirements

• BE/MTech/MS/PhD with 10+ years of ASIC verification experience.
• Experience in ARM processor-based design verification
• Experience in Verilog, System Verilog, UVM/OVM, Scripting languages like Perl/Python etc