Job Purpose:
You’ll be working for Dialog Semiconductor, one of the fastest growing Semiconductor companies in Europe, so you’ll get exposure to a high performing, fast paced and global business.
Principal Accountabilities:
- Define testbench infrastructure using SystemVerilog, UVM and Formal.
- Responsible for complete digital level verification.
- Modeling of analog functions in SystemVerilog.
- Responsible for complete chip level verification of mixed signal IC.
- Work closely with design team to architect a new design verification environment and produce high quality verification closure.
- Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
Requirements
- 10+ years of experience in ASIC/IC verification.
- Experience in UVM based verification flow.
- Good understanding of OOP concepts
- Familiar with scripting language like Makefile, Perl, Tcl or Python.
- Experience in SimVision or Verdi debug skills.
- Experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking) is a plus.
- Experience in UVM based verification flow.
- Good understanding of OOP concepts
- Familiar with scripting language like Makefile, Perl, Tcl or Python.
- Experience in SimVision or Verdi debug skills.
Renesas Electronics
Renesas is a top global semiconductor company developing products for automotive, industrial, infrastructure, and IoT markets.
Other jobs at Renesas Electronics
Why OmniJobs?
- Rare & hidden jobs
- New jobs every day
- No expired job posts
- All jobs in English
Receive emails about similar jobs
Get alerts to your inbox about new open jobs that are similar to this one.
No spam. No ads. Unsubscribe anytime.
Similar jobs