Associate Engineer - RTL Design

• Understanding the RTL design and Uarch of IPs and integrating them in sub-systems or SoC
• Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc.
• Design for Testability (DFT) checks
• Close collaboration with different domain teams

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 0-3 years of IP/SoC Design Experience
• Experience in SoC design and integration for complex SoCs is a must.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Should have knowledge of AMBA protocols - AXI, AHB, APB besides SoC clocking/reset architecture.
• Strong RTL design and coding experience in Verilog, system Verilog, VHDL etc.

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