Principal Engineer - ASIC development Engineering

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise.

ROLES AND RESPONSIBILITIES:

• Understanding of DFT Architecture and SoC development flows
• Leading different DFT tasks and providing solutions for DFT problems.
• Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs.
• Working closely with the internal DFT team and ensure timelines and quality of deliveries are met.
• Work closely with the Product Engineering team and understand the test requirements, get involved in silicon debugs.
• Continuously monitor the enhancement needs on internal DFT and ensure all flow requirements are implemented by CAD.

Requirements

• B.Tech / M,Tech / Phd in Electronics, Computer science or Electrical Engineering
• Minimum 9 years of experience in DFT
• Strong understanding of DFT Architecture

SKILLS:

• Experience in SoC DFT architecture, DFT IP development and DFT methodology.
• Proven track record of driving DFT architecture convergence in semiconductor designs.
• Work independently on multiple DFT problems across different projects.
• Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs).
• Proficiency in SCAN, MBIST implementation.
• Solid understanding of JTAG & BSDL standards.
• Good understanding on Test clocking requirements, Test mode timing closure.
• Proficiency in silicon debugs, Shmoo analysis, and understand Test engineering requirements.
• Capable of setting up MBIST, ATPG and Simulation environments and debug issues independently.
• Good understanding of test constraints and support the STA teams for test mode timing closure.
• Capable of translating test requirements into Test IPs and pioneer any new test hardware implementations.
• Provide training and mentorship to the team as needed.
• Good analytical and problem-solving skills.
• Strong communication skills and the ability to work effectively in cross-functional teams.

Additional information

Western Digital is committed to providing equal opportunities to all applicants and employees and will not discriminate based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the Equal Employment Opportunity is the Law poster.

Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

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