Physical Design Engineer

In an environment of growth and new product development we seek to strengthen our design team with a Physical Design Engineer.

Our team is involved in the transformation of a functional description into working modules in Systems on Chip (SoC). Our work is starting from an RTL description and additional SOC requirements such as module frequency specifications, Design-For-Test (DFT) methodology used, where to place external signals. Our team selects the libraries to apply, transforms the functional RTL description into structural building blocks, distributes them on a digital representation of the silicon area and checks if all power and timing conditions can be met. Intensive interaction with frontend, DFT, and SoC-physical implementation is a must. The physical-aware representation of the result is fed back into the SoC and will be re-usable on further SoCs in the ideal case.

In your new role you will work on physical implementation of small, but highly sophisticated building blocks for SoCs. Starting with synthesis there will follow placement, clock tree and DFT insertion, routing, and timing analysis. You will run through all steps and will become a generalist or may focus and specialize on certain steps.

Your profile:

• Bachelor or Master in Electrical Engineering
• Fluent English and the ability to work within international teams are required

The ideal candidate should have skills in one or more of the following areas:

• RTL-to-Gate Level synthesis
• Constraining of circuit timing
• Interface to design front-end to review constraints, suggest RTL changes in timing-critical paths
• Static Timing Analysis (STA)
• Implement and analyze clock trees
• Optimization for low power consumption
• Floor-planning and manual layout knowledge
• Analysis of signal integrity and IR drop
• TCL, Pearl or Python knowledge
• Experience with UNIX / Linux environment

More information about NXP in Germany...