Senior Staff Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Group Description
Marvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production.

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

What You Can Expect

ASIC Design Engineers are responsible for designing, verifying, and evaluating digital circuits in high-speed data communication ICs. In this role, you will contribute to verification plan development, test environment setup, modeling, test case development, and execution.

As a senior team member, you will focus on enhancing design verification methodologies and workflows. You will collaborate cross-functionally with analog and DSP teams to achieve high-quality analog mixed-signal verification. Key responsibilities include, but are not limited to:

• Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
• Use and improve UVM DV environment.
• Improve the design methodology and flow.
• Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Provide the support to the product teams, for both pre- and post-silicon

What We're Looking For

• MS in Electrical Engineering with 8+ years of relevant experience.
• Strong communication skills and a collaborative team player.
• Motivated, hardworking, and eager to contribute to a highly skilled design team. Effective communication and leadership skills, with experience working in a global team.
• Solid understanding of fundamental concepts in digital logic design.
• Knowledge of ASIC verification flows and methodologies.
• Proficiency in Verilog, SystemVerilog, and UVM.
• Experience with UNIX shell scripting (Csh, Bash).

Preferred skills:

• Experience working with Verification IPs (VIPs).
• Knowledge of formal verification.
• Familiarity with low-power design techniques.
• Proficiency in MATLAB and C/C++ for system simulation and evaluation.
• Knowledge of DSP function hardware implementation.
• Strong scripting skills in Perl and Python.

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Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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