Senior Staff Analog Layout Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Central Engineering Foundational IP team is responsible for Layout design of SerDes IPs and Foundational IPs

What You Can Expect

• As a key member of Marvell's Central Engineering team, you will play a leading role on developing next-generation high speed SerDes IPs.
• To work with leading edge finfet technologies to produce best-in- class analog IPs which enable us to move, store, process and secure the world's data faster and more reliably than anyone else.
• Effectively communicate with Design Engineers to clarify and realize the layout requirements based on the schematic functions.
• Provide feedback to Circuit Design Engineers on any modifications to schematics after layouts are completed.
• Interact with the Physical Verification (PV) team to analyze DRC/LVS/ANT/ERC results and achieve PV closure. ​

What We're Looking For

• Bachelor's or Master's Degree and or PhD in Electrical/Electronics Engineering, Microelectronics or related fields and 8+ years of related professional experience.
• Good understanding of advanced semiconductor technology process and device physics.
• Full-custom circuit layout/verification and RC extraction experience.
• Experiences in one or more of the following area is preferable : Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc.
• Should have good knowledge of CMOS process and fabrication
• Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc).
• Experiences in advanced technology node under 32nm/28nm/16nm/14nm and FinFET is preferable.
• Experience with EMIR analysis, ESD, antenna and related layout solutions.
• Good communication skills and willingness to work with global team.
• Good learning ability, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
• Programming skills, automation and circuit Design background is a plus

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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