At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Join us in the development of Pegasus, our next-generation massively parallel DRC (Design Rule Check) product! Your role will be analyzing how our EDA tool, Pegasus, performs in customers’ most complicated IC designs, studying the culprit of tool misbehavior and performance bottlenecks, and propose enhancements based on your observations at customer site. Along the way, you will be trained to evaluate a tool not just by 1 or 2 core algorithms, but by the infrastructure design, the whole program flow, and the interaction between software and hardware.
To apply for this position, you will be required to
- Be familiar with C++, Python, or any other object-oriented programming language. Prior experience of developing large project is a plus.
- Have good English reading and writing skills, so you will be able to communicate your thoughts and findings with R&Ds located at other sites around the globe.
In 3 years, we hope you will …
- Gain a bird’s-eye view of Pegasus’ infrastructure, including its pipelined-stream technology and distributed computation, and how to optimize it in user’s environment.
- Be able to share technical details of Pegasus with colleagues from other departments (product engineers, QA engineers, etc.) in Taiwan.
- Be a team player!
We’re doing work that matters. Help us solve what others can’t.
Cadence Design Systems
Leader in hardware emulation-acceleration technologies and products
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