Senior Staff Physical Design Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the timing/physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

• In this hybrid role based in Westborough, MA, you will work with a global team on both the timing (preferred) or physical design of complex chips as well as the methodology to enable an efficient and robust design process.
• You will be responsible for maintaining, enhancing, and supporting Marvell's Timing or Place and Route Flows, leveraging industry-standard EDA tools.
• Your tasks will include performing synthesis, place and route, and/or timing analysis and closure on multiple intermediate and complex logic blocks.
• You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.
• Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level.
• This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What We're Looking For

To be successful in this role you must have:
Completed a Bachelor’s Degree in Electrical/Computer Engineering, Computer Science, or related fields and have 5-10 years of related professional experience OR a Master’s degree and/or PhD in Electrical/Computer Engineering, Computer Science, or related fields with 3-5 years of related professional experience.

• Good understanding of standard RTL to GDS flows and methodology
• Good scripting skills in languages such as Perl, tcl, and Python
• Good understanding of digital logic and computer architecture
• General knowledge of Verilog/VHDL
• Experience with ASIC or processor-style design flow and timing closure.
• Understanding of current design technologies used in major foundries is desired.
• Good communication skills and self-discipline contributing in a team environment

Requirements for STA role:

• Strong user of Synopsys PrimeTime (or other equivalent timing tool) including these skills:

○ translating design timing requirements into SDC

○ accurate evaluation of PrimeTime timing reports to identify solutions to timing issues

○ extracting relevant timing data from timing runs interactively

○ Strong knowledge of several key static timing analysis concepts which can include crosstalk analysis, timing of I/O interfaces, statistical modeling, scan timing, global clock balancing, etc.

• Proven track records of executing chip or partition level timing analysis and closure activities and taping out complex SOC chips under tight schedule pressure.

• Experience in developing, supporting or contributing to chip-level timing flow definition is highly desired.

Requirements for PD role:

• Experience with Industry standard PnR tools such as Innovus (preferred)

• Experience with 6 or more of the following:

• Tops-down hierarchical floorplanning
• Route planning and routability issue resolution
• Power grid design and validation
• Various clock synthesis schemes
• SI, EM/IR, complex DRC rules
• Power intent and implementation of multiple power domains
• High speed and low power implementation techniques/trade-offs
• Gate-to-gate equivalence checking
• Parasitic extraction

• Proven track record of executing chip, subsystem or block-level physical design work and taping out complex SOC chips under tight schedule pressure.

• Experience in developing, supporting or contributing to chip-level PD flow definition is highly desired.

#LI-TM1

Expected Base Pay Range (USD)

136,900 - 202,580, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.