Senior Staff Test Engineer

As a Staff Test Engineer in the Renesas Radio Frequency Division, you will play a critical role in developing and executing comprehensive test solutions for our cutting-edge RF ICs. This role requires a strong understanding of RF principles, extensive experience in RF IC test development on test platforms such as Advantest 93k.

Primary Responsibilities:

• Develop, implement and optimize RF test methodologies for our sub 8 GHz RF ICs such as driver amplifiers, LNAs, DVGAs, High performance Switches.
• Participate in development of test plans and test strategies (Definition of tester configurations, socket selection and validation planning, test roadmaps)
• Manage test-related documentation including test procedures, technical drawings, and reports.
• Drive ATE load board hardware development from test plan all the way to fab and assembly.
• Perform ATE bring-up using GRR methodology as well as other best practices.
• Optimization of hander settings for best RF performance
• Support bench to ATE correlation.
• Analyze test data to assess test robustness.
• Work with OSAT partners to release test solutions at our high-volume test locations.
• Spearhead cost reductions through yield improvement and test time optimizations
• Assist excursion management (Low yield and RMAs)
• KPI reporting
• Continuously identify enhancements to the test development process, focusing on efficiency and reduction of overhead
• Act as a mentor to junior team members, fostering technical and professional growth

Requirements

• BSEE or equivalent and 5+ years of Product Development experience
• Expertise bringing up RF ATE test solutions using Advantest 93k platform (SMT7, SMT8, RF8, PS1600, AVI64, DPS64, DPS128) for new products from definition to production release.
• Experience in RF theory and application.
• Knowledge of operation and testing of RFIC and mixed signal products for cellular and satellite applications.
• Advanced knowledge in IC manufacturing process.
• Proficiency using RF test equipment such as Oscopes, SPA, VNA, Power sensors, Sig Gen.
• Understanding of SPI, I2C, I3C protocols
• Experience implementing SCAN and BIST
• Implementation of OTP and Performance calibrations at test
• Statistical analysis capability. Knowledge of JMP, Gauge R&R, limit setting and DOE methodology (preferred)
• Ability to manage complex projects in parallel and to schedule
• Good critical thinking skills to troubleshoot a variety of challenging issues
• Good communication, team working, and interpersonal skills are a must