Staff ASIC Digital Verification Engineer

Staff ASIC Verification Engineer with some design experience.

• ASIC Design Verification and Development

  • Verify the design with constrained random stimulus
  • Possibly aid in the design, development, and bench validation of ASIC hardware components.
  • Participate and contribute to an agile chip development flow

• Technical Proficiency:

  • Utilize UNIX operating systems for design and development tasks.
  • Employ UVM verification techniques and tools for efficient hardware development.
  • Use simulation tools to verify design integrity and performance.
  • Run regressions, collect code coverage and functional coverage

• Documentation and Reporting:

  • Prepare and present regular status reports to management and stakeholders.

Requirements

• 4+ years of practical design and verification experience using SystemVerilog UVM and ASIC verification.
• Experience with Synopsys and/or Cadence simulation tools.
• RTL and possibly Gate level debug of mixed-signal ASICs including analog models.

Desireable Skills

• RTL Design
• Automotive chip verification flow
• JIRA