Job Details:

Job Description:

We are looking for Physical Design Engineers with strong RTL2GDSii Skill. Job responsibilities include Logic Synthesis, Floor-planning, Place and Route, Timing Analysis, Convergence, IR/EM analysis, Formal verification, VC-LP, DRC/LVS clean-up and delivery of the Blocks or Subsystem to SOC level that is essentially complete RTL2GDSii vertical execution skill. Desirable to have strong experience in full chip implementation or flow development experience.

Qualifications:

• The right candidate must have around 10-15 years' experience after B.S. or 10 years after Master's degree.
• Candidate must have owned and closed large design blocks of size 2-3Million, High performance design more than 1.5G frequency and should be experience very deep submicron nodes i.e. 7nm or below.
• Candidate should be experienced in Synopsys Tool suite or Cadence Tool Suite such as DC, ICC2/Fusion/Innovus, Primetime or alternative, Calibre/ICV, Conformal/Formality, ..etc.
• In addition, expertise in Ansys Redhawk-SC is highly desirable.
• The person should have right mindset and ability to handle dynamic changes in RTL. Automation skills in TCL/Perl/Python a...