We are looking for Senior Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. Youโll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Basic qualifications
- Strong academic and technical background in electrical engineering. At minimum, a Bachelorโs in EE is required, and a Masters is preferred.
- โฅ3 yearsโ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
- Entrepreneurial, open-minded behavior a...
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Astera Labs
Global leader delivering semiconductor-based connectivity solutions for high-value artificial intelligence and machine learning applications with offices in Taiwan, China, Vancouver, Toronto, Canada, Haifa, Israel
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