Digital Verification Engineer

Renesas is looking for a Mixed-Signal Verification Engineer to join our team of engineers that support the development and release of several power management ICs for the portable market. Come join a team that demonstrates that a potential product operates as specified and help to find issues and mitigate them before the product is manufactured.

Requirements

• BS or MS in Electrical Engineering or equivalent
• 8+ years of experience in product development
• Experience with creating and/or using real-numbered models in modeling languages such as SystemVerilog
• Familiar with EDA design tools and Cadence design environment
• Good communication, organizational, and teamwork skills with the ability to take ownership and help to ensure that a task is complete on time
• Developing a list of tests from the datasheet to determine chip coverage
• Creation and maintenance of testbench and design files for simulation regression runs
• Delegation of tests to a group of verification engineers and assist with troubleshooting
• Provide technical assistance and mentoring to others as needed
• Demonstrating ownership and completion of the verification of several portions of an IC.
• Familiarity with scripting language like Makefile, Perl, Tcl or Python
• Experience in UVM based verification flow is a plus
• Local to the Phoenix AZ area preferred, relocation to AZ or remote work optional for well qualified candidates.