Principal Test Technology Architect

Operations Engineering Division (OED) is the central pillar organization that supports all Product Groups/Business Divisions and other support organizations including Sales and Marketing and Business Operations teams such as Supply Chain Management and Procurement. This organization offers a solid central platform managing all test technology for both Internal and External Manufacturing for the whole company.

Duties and Responsibilities: Assess and support of Test Technology for Renesas embedded processing (EP) and high performance computing (HPC) groups. Closely collaborate with product groups, and test operations teams to ensure that Renesas strategic requirements for profitability, growth and operations portfolio will be met. The new hire is expected to:

• Interface into product lines within EP and HPC groups to identify emerging technologies and commercial targets for tester, handler, prober roadmaps.
• Define and drive test technology roadmap in support of corporate level roadmap that optimizes capability, commercial and operational aspects of production test thru liaison with technical leadership within product groups, operations, procurement, suppliers, vendors.
• Ensure infrastructure for test technology roadmap is enforced and in place at all production test sites working closely with test internal operations team.
• Execute industry bench-mark studies to ensure Renesas test roadmap is best in class for commercial, supply and technical metrics
• Collaborate with Renesas community to identify innovative and efficient production test techniques for power analog and mixed-signal ICs with sharing on approaches thru load board design, DFT, SW QA, WT/FT participation, SLT, strip-test, KGD, discretes, production BI, test flow optimization, test quality.
• Establish and maintain test cell database for EP and HPC products on OED sharepoint (vendor relations, BD support, specifications on tester roadmap selection, ROI for investment, internal/OSAT optimization, technology roadmap executive reports.
• DRI for Test Technology (EP/HPC) in the test HW and SW councils.
• Travel required to meet with production lines (primarily US/EU/UK/JPN), ATE vendors (primarily SJ) and OSATs (Primarily APAC).

Requirements

• Master’s degree in Electrical Engineering, function-related discipline, or equivalent experience.
• 10 years’ experience working in semiconductor Operations or Engineering.
• Proven track record in ATE test development for mixed signal IC.
• Thorough understanding of mixed-signal design blocks, topologies, and associated test concepts.
• Ability to take decisions and to prioritize work.
• Ability to work under pressure and with multi-site, multi-national teams.
• Excellent interpersonal, organizational and communication skills.
• Proven track record of technical lead functions in semiconductor test with technical depth.
• Bilingual capability with skill English + Japanese/Chinese.