Senior Physical Design Engineer

Overview
We are looking for a Sr Staff Engineer to support the Back End Physical Design aspects of high-performance compute SOC/MCU development. The candidate is expected to be hands-on and have intermediate level knowledge on advanced technology node back-end physical implementation, preferably with sign-off and tape-out experience in automotive grade SOCs.

Responsibilities

• Contribute to advanced technology node physical implementation and sign-off domains.
• Contribute to improve the process, methods and tools, driving the SOC chip development for lowest possible AUC (average unit cost) and highest yield quality
• Contribute to Chip KPIs on Power, Performance, Area, Thermal & Schedule commitments are met predictably and consistently.

Requirements

• At least 7+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits.
• Conversant on EDA tools such as Cadence iSpatial, Fusion Compiler, Redhawk, Primetime, Tempus, Conformal/Formality etc. is a plus
• Expected to have intermediate level knowledge on E2E physical implementation flows such as Synthesis, Floorplan, Placement, CTS, Route/ECOs using industry standard tools.
• Familiarity with STA, PDN, PDV, Logic ECOs and Chip Sign-off is a plus
• Must be cognizant about low power implementation techniques.
• Can – do attitude; openness to new environment, people and culture
• Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus.
• Strong drive & ability to coordinate work across a cross functional, highly experienced global team.
• Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science