Verification Engineer

Renesas is looking for a Verification Engineer for our RadHard development team. This team develops high performance, radiation-hardened integrated solutions.
The environment is fast paced and team members are empowered to make decisions within the scope of their job function. The successful candidate will be responsible for
both developing and maintaining the top-level, AMS (mixed signal) verification environment and helping with the digital sub-block verification environments (UVM, constrained random).

Job Responsibilities:
• Actively involved in understanding the design from the specification phase, both for functional testing and for test mode/ATPG testing.
• Creating AMS and SystemVerilog models for analog functions.
• Defining testbench infrastructure using SystemVerilog, UVM, assertions and formal verification.
* Creating digital verification modules and IP that can also be ported to the top-level mixed signal verification environment.
• Owns the overall chip verification plan and strives for maximal verification coverage in the most time efficient manner.
• Works diligently to accomplish project goals and meet schedule requirements.
• Drives towar...