Scope of Responsibilities / Expectations
- Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production.
- Ensure Test Coverage Goals are met at SoC Level.
- Addressing test quality targets in DFT architecture and test pattern generation.
- Leading various aspects of Test architecture including Scan&ATPG, and post-silicon support
- Work with different functions like front-end design, verification and physical design to ensure production quality silicon.
- Support post-silicon activities, working with test engineering and validation teams.
Specific Knowledge/Skills
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Master/Bachelor's Degree in Electrical/Electronic Engineering.
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Experience of 12+ Years in DFT with successful delivery of production quality chips.
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Senior SoC DFT engineers, with experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
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Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
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Self-motivated. Excellent written and verbal communication skill.
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Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
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Should be a team player and willing to work with cross functional teams in issues resolution.
FR NXP Semiconductors France SAS
NXP is a semiconductor company specializing in secure connectivity solutions.
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