Principal Engineer - ASIC Development Engineering

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise.

ROLES AND RESPONSIBILITIES:

• Understanding of DFT Architecture and SoC development flows
• Leading different DFT tasks and providing solutions for DFT problems.
• Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs.
• Working closely with the internal DFT team and ensure timelines and quality of deliveries are met.
• Work closely with the Product Engineering team and understand the test requirements, get involved in silicon debugs.
• Continuously monitor the enhancement needs on internal DFT and ensure all flow requirements are implemented by CAD.

Requirements

• B.Tech / M,Tech / Phd in Electronics, Computer science or Electrical Engineering
• Minimum 9 years of experience in DFT
• Strong understanding of DFT Architecture

SKILLS:

• Experience in SoC DFT architecture, DFT IP development and DFT methodology.
• Proven track record of driving DFT architecture convergence in semiconductor designs.
• Work independently on multiple DFT problems across different projects.
• Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs).
• Proficiency in SCAN, MBIST implementation.
• Solid understanding of JTAG & BSDL standards.
• Good understanding on Test clocking requirements, Test mode timing closure.
• Proficiency in silicon debugs, Shmoo analysis, and understand Test engineering requirements.
• Capable of setting up MBIST, ATPG and Simulation environments and debug issues independently.
• Good understanding of test constraints and support the STA teams for test mode timing closure.
• Capable of translating test requirements into Test IPs and pioneer any new test hardware implementations.
• Provide training and mentorship to the team as needed.
• Good analytical and problem-solving skills.
• Strong communication skills and the ability to work effectively in cross-functional teams.