🇧🇬 Bulgaria
Software development
AgileCadence simulation toolsCadence VirtuosodebuggingDFTFormal Equivalence toolsJIRAmixed-signal designPLLsRTL DesignSTASynopsys
Staff ASIC Design Engineer with Mixed Signal IC Experience
Requirements
- 8+ years of practical design experience in a mixed signal/analog-on-top flow
- RTL Design
- Experience with mixed-signal design modelling and debugging.
- Experience with Synopsys and/or Cadence simulation tools.
- Experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools.
- RTL and Gate level debug of mixed-signal ASICs.
Desireable Skills
- Cadence Virtuoso
- Knowledge of PLLs.
- Automotive chip design flow
- JIRA
Renesas Electronics
Renesas is a top global semiconductor company developing products for automotive, industrial, infrastructure, and IoT markets.
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🇧🇬 Bulgaria
Software development
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