Full Chip Layout Lead

Our VLSI Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility. Each Physical Design engineer has an end-to-end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges. We do not consist of a CAD team & each engineer may have vertical & horizontal domain ownership allowing personal development and a meaningful contribution & impact on the entire team. Our SoC products are new & 1st generation of their kind, co-designed along with package & board teams. Full Chip, subsystems & blocks floorplan & RTL design are brand new, providing new challenges & interesting work environment. Leading Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out. Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level. IO Pad, Bump, RDL & ESD planning & implementation, co-designing with Package & Board. Involved in chip architecture, in close collaboration with the design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence. Physical verification owner, defining Physical Verification methodologies & activities for Full Chip, Sub System & Block Level. Working with engineers to identify and overcome roadblocks and obstacles.

• Competitive salary
• Hybrid work environment
• Opportunity to work on 1st generation SoC products
• Meaningful contribution and impact on the entire team

• BSc/MSc in Electrical Engineering/Computer Science.
• 8 years of experience in VLSI backend (RTL2GDS).
• 5 years of experience in Full Chip Integration & verification on complex SoCs.
• Expert knowledge in floor planning, integration & signoff methodologies for hierarchical designs.
• Physical Verification Expert (DRC/LVS/PERC).
• Experience with IO Pad, Bump & ESD planning.
• Experience in technically leading complex backend activities, preferably of complete SoC's.
• Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration & Physical Signoff).