Associate Digital Engineer

The team is performing verification for system IP (such as clock pulse controller(CPG), system controller (SYSC)) as the below steps:

• Make DRBFM, target specification, implementation specification.
• Perform UT and CT verification.
• Generate and verify UPF (Unified Power Format)

Requirements:

• Have 1+ year of experience in the verification.
• Good knowledge about verification (UT, CT).
• Familiar with simulator/debuger VCS/Verdi/XLM/Indago
• Have knowledge about Verilog and UPF.
• Basic knowledge about Formal verification, SVA, TCL
• Knowledge about SystemVerilog, UVM or Python is a plus.
• Provide transparent information, be agile at daily operation.
• Communicate fluently with teams and customer as a global mindset.
• Be innovative with excellent idea in design and/or work-process optimization.

Requirements

• Bachelor or Master's degree in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics – Computer Science, Physics – Electronics, and Physics – Computer Science