Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities:

• Development, automation and maintenance of EDA flows and scripts for physical implementation
• PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, such as 7nm/5nm/3nm/2nm
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs
• Digital design implementation using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools
• Participate in benchmarking PPAs for customer engagements

Required skills –

• Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes
• 3 to 7 years of relevant experience in ASIC design environment
• Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis and Formal Verification
• Experience with Cadence digital design tools will be an added advantage
• Hands on scripting languages like Python, Perl, TCL, Unix shell etc
• Strong understanding of digital logic design, processor design, and computer architecture is desirable
• Should have excellent communication, analytical and problem solving skills
• Should be able to technically lead and guide the team members
• Should be self-motivated and good team player

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