Senior Memory IP Design Engineer

The Allegro team is passionate about providing intelligent solutions that move the world toward a safer and more sustainable future. With more than 30 years of experience developing advanced semiconductor technology, innovation with purpose touches every aspect of our business. From customer engagement and employee recognition to technology advancement and serving the local communities in which we maintain offices, innovation consistently drives our mission and definition of success.

SUMMARY

Join a global leader in sensing and power solutions that's driving the future of technology! At Allegro MicroSystems, we're passionate about innovation (Allegro 3.0!) and creating cutting-edge semiconductor solutions that make the world safer, smarter, and more sustainable. As a Senior Memory IP Design Engineer, you'll play a critical role in developing and verifying the high-performance memory IP that forms the foundation of our industry-leading products. You'll collaborate with a talented team of engineers to design, test, and deliver robust memory solutions that meet the demanding requirements of automotive, industrial, and consumer applications. If you're a highly motivated and experienced engineer who thrives in a fast-paced, collaborative environment, we encourage you to apply!

WHAT YOU'LL DO

• Design and verify a range of standard IP memories, including Single-Port SRAM, Register File, ROM, One-Time-Programmable, EEPROM, and FLASH, ensuring they meet the highest standards of performance, area efficiency, and power consumption.
• Develop robust NVM, VM, and driver circuits, as well as digital IP, to create comprehensive memory solutions optimized for Allegro's target applications.
• Drive the successful implementation of memory IP in silicon, collaborating closely with layout engineers and utilizing your expertise to ensure smooth integration and optimal performance.
• Lead the characterization and standardization of memory/digital IP for global design use within Allegro's custom PDK environment, enabling efficient design reuse and consistency across projects.
• Develop comprehensive documentation and application use cases for memory IP, empowering design teams worldwide to leverage your creations effectively.
• Contribute to the development and execution of silicon test and validation plans, ensuring the reliability and robustness of Allegro's memory IP in real-world applications.
• Collaborate with design teams on memory debug and diagnostics, providing your expertise to resolve issues and ensure the timely delivery of high-quality products.

ESSENTIAL REQUIREMENTS

• BSEE or MSEE degree in Electrical Engineering or a related field.
• 5+ years of experience in memory and mixed-signal transistor-level design, circuit verification, and silicon testing.
• Proven ability to design and verify a variety of memory architectures, including SRAM, ROM, EEPROM, and FLASH.
• Strong understanding of CMOS fabrication methods and their impact on circuit design and performance.
• Expertise in layout parasitic/leakage design trade-offs and optimization techniques.
• In-depth knowledge of digital components, including logic, memory, EEPROM, TAP controllers, JTAG, FPGA, serial data communication protocols, microprocessors, and microcontrollers.
• Proficiency in developing memory test/validation plans and characterizing memory/standard cells in standard liberty format.
• Familiarity with modeling challenges for sub-micron technologies.
• Hands-on experience with Cadence tool flows, including Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre.
• Solid understanding of HDL languages (Verilog, VerilogA, and VerilogAMS). Experience with Skill, C, and SystemVerilog is a plus.
• Strong understanding of device physics at the transistor design level (cross-section, STI, DTI).
• Excellent written and verbal communication skills.