STA Engineer

• Static timing analysis and timing closure (TOP and block).
• Propose technical solution to enhance the design from RTL to GDS to achieve timing closure.
• Collaborate with FE/BE teams to finish chip design within definited schedule.

Requirements

• Have 2 years of experience in STA position
• Bachelor or Master Degree in Information Technology/Computer Engineering/Computer Science/Telecoms/Electronics or similar.
• Experienced in Timing closure & tape out projects.
• Understanding of PnR design, CTS design & Sign-off.
• Have knowledge in logic related design activitíe (clock design, system control design, synthesis, RTL design, DFT design,...) is a plus point.
• Solid knowledge in using EDA tool (Synopsys, Cadence,...)
• Good written and oral communication (in English) & interpersonal skills
• Strong team-oriented working and good relationship-building with others
• Long-term working commitment