Principal DFT Engineer

Perform semiconductor engineering design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry. Responsible for handling RTL design for DFT related changes in both subsystem level and top level designs. Insert TAP, IOs, Test Pinmux using DFT flows and MBIST RTL for memories and verifying them. Analyze scan DRCs and ensure issues are resolved in RTL. Perform analysis on ATPG reports on coverage and devise mechanisms to improve coverage and generating patterns for ATE. Responsible for the regression suite for both non-ATP and ATPG simulations through RTL/GLS simulation bring up. Collaborate with Product and Test Teams to bring up patterns on wafer prob and on final test. Confer with customers and other departments on design status, processing, testing and technical issues, and failure analysis, and he/she will monitor production of products and devices to ensure conformance to design specification.

Qualifications:

Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI Design and Microelectronics, foreign equivalent or related field.

Five (5) years of experience in job offered, Engineer, ASICS SFT Engineer, Technical Lead or related occupation.

Required skills:

Position requires five (5) years of experience in:

• RTL & Gate level simulation;
• Block level Scan insertion;
• ATPG pattern generation;
• MBIST Insertion;
• DFT Timing Checks,
• Simulations;
• DFT validation and DFT RTL Integration; and
• Verification.

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.